Asymptotically Zero EnergySplit - Level Charge Recovery

1 As the clock and logic speeds increase, the energy requirements of CMOS circuits are rapidly becoming a major concern in the design of personal information systems and large computers. Earlier, we presented a new form of CMOS Charge Recovery Logic (CRL), with a power dissipation that falls with the square of the operating frequency, as opposed to the linear drop of conventional CMOS circuits 1]. The technique relied on constructing an explicitly reversible pipelined logic gate, where the information necessary to recover the energy used to compute a value is provided by computing its functional inverse. Information necessary to uncompute the inverse is available from the subsequent inverse logic stage. In this paper, we present a new and greatly sim-pliied form of CRL, we call it Split-Level CRL (SCRL). Using split-level voltages, SCRL diiers from our original CRL in that it needs only 2, instead of 16, times as many devices as conventional CMOS, requires only one wire for every signal, instead of 4, and actively drives all outputs during sampling. Furthermore, we will show how to construct SCRL circuits using only 2 external inductors for every chip. Depending on the Q of available inductors, we anticipate energy savings of over 99% per logic operation for logic which is clocked suuciently slowly.